1. Field of the Invention
The present invention relates generally to analog-to-digital converters, and more specifically, to an analog-to-digital converter having a serialized quantizer output.
2. Background of the Invention
Delta-sigma analog-to-digital converters (ADCs) are in widespread use in consumer and industrial devices. Delta-sigma ADCs provide a very linear response and control of quantization noise. The relative simplicity of the architecture and the ability to finely control the quantization noise makes delta-sigma converter implementations very desirable. The delta-sigma modulator based analog-to-digital converter includes a loop filter that receives an input signal and a quantizer that converts the output of the loop filter to a digital representation. Feedback from the quantizer output is applied to the loop filter in feedback modulator topologies or is summed with the output of the loop filter in feed-forward modulator topologies to provide a closed-loop that causes the time-average value of the output of the quantizer to accurately represent the value of the modulator input signal. The loop filter provides shaping of the quantization noise at the output of the quantizer in response to the feedback signal applied from the quantizer to the loop filter. The feedback provided from the quantizer is typically generated by a coarse feedback DAC that receives the digital output of the quantizer and generates an analog value that is provided to the loop filter or the output summer.
The output of the delta-sigma ADC is generally the output of a decimation filter that is provided at a rate substantially lower than the quantization rate of the quantizer. The output decimated samples are usually provided in either a parallel or serial form. However, the input to the decimation filter, which is the output of the quantizer, is typically provided in a parallel form if the output of the quantizer has more than two levels. Since a typical quantizer may have, for example, seventeen levels, a serial bit stream at five times the quantization rate would be required to transfer the quantizer output using a typical serial interface. In some applications, for example in isolated circuits such as transformer-coupled or optically-isolated circuits, it is desirable to couple the quantizer output using a serial interface in order to transfer the data from the quantizer output to the serial interface over a single channel. However, the increased data rate required in an ADC having a number of quantizer levels greater than two comes with increased power requirements, increased component bandwidth requirements and higher generated levels of electromagnetic interference (EMI) due to the higher bit rates required.
Therefore, it would be desirable to provide a delta sigma ADC that has a serialized quantizer output without requiring a high serial data rate.